Chemical-mechanical polishing is used increasingly as a planarizing technique in the manufacture of VLSI integrated circuits. It has potential for planarizing a variety of materials in IC processing but is used most widely for planarizing metallization layers and interlevel dielectrics on semiconductor wafers, and for planarizing substrates for shallow trench isolation.
In trench isolation, large areas of field oxide must be polished to produce a planar starting wafer. Integrated circuits that operate with low voltages, i.e. 5 volts or less, and with shallow junctions, can be isolated effectively with relatively shallow trenches, i.e. less than a micron. In shallow trench isolation (STI) technology, the trench is backfilled with oxide and the wafer is planarized using CMP. The result is a more planar structure than is typically obtained using LOCOS, and the deeper trench (as compared with LOCOS) provides superior latch up immunity. Also, by comparison with LOCOS, STI substrates have a much reduced "birds' beak" effect and thus theoretically provide higher packing density for circuit elements on the chips. The drawbacks in STI technology to date relate mostly to the planarizing process. Achieving acceptable planarization across the full diameter of a wafer using traditional etching processes has been largely unsuccessful. By using CMP, in which the wafer is polished using a mechanical polishing wheel and a slurry of chemical etchant, unwanted oxide material is successfully removed with a high degree of planarity.
In multilevel metallization processes, each level in the multilevel structure contributes to irregular topography. In three or four level metal processes, the topography can be especially severe and complex. The expedient of planarizing the interlevel dielectric layers, as the process proceeds, is now favored in many state of the art IC processes.
Planarity in the metal layers is a common objective, and is promoted by using plug interlevel connections. A preferred approach to plug formation is to blanket deposit a thick metal layer on the interlevel dielectric and into the interlevel windows, and then remove the excess using CMP.
Thus, in a typical case, CMP is used for polishing an oxide, such as SiO.sub.2, Ta.sub.2 O.sub.5, W.sub.2 O.sub.5. It can also be used to polish nitrides such as Si.sub.3 N.sub.4, TaN, TiN, and conductor materials used for interlevel plugs, e.g. W, Ti, TiN.
Since CMP is at least partly an abrading process, friction between the polishing wheel and the substrate causes heating. In some cases the heating may be substantial, and may cause undesirable process variations. The chemical parameters in the process, e.g. etch rates, vary with temperature. Some CMP processes, e.g. tungsten CMP, are exothermic, which may further aggravate heating problems. Significant temperature variations across the wafer surface during polishing therefore may result in uneven polishing, and unacceptable variations in the thickness of the polished layers.
It has been proposed to control the temperature of the polishing platen to control excessive heating. However, this proposal does not address, and cannot solve, problems due to temperature variations across the surface of the substrate being polished.